A principle challenge in performing measurements is to accurately remove the effects of the test fixture. Copper Mountain Technologies presents a simplified way to automatically remove the fixture effects to characterize SMD components using advanced algorithms with a Vector Network Analyzer.
This session will showcase Analog Devices' Stingray analog and hybrid beam-forming RF development kit. Focusing on the RF section of an X/Ku band phased array system, the developer's kit consists of 32 TR Modules (ADTR1107), arranged in a 10 GHz lattice spacing, and driven by 8 4-channel beam-former ICs (ADAR1000). Snap-on antenna boards can be attached to facilitate over-the-air testing. Alternatively, with the antenna boards removed, the system can be electrically tested. Results of electrical and Over-the-Air testing will be presented.
In the last decade, there has been a significant increase in wireless data requirements, resulting in a demand for high bandwidth, multi-Gbps, short-range wireless applications. Efforts by consortiums, such as WiGig and IEEE 802.11ad, to establish a 60 GHz wireless ecosystem would increase consumer product development for this market exponentially. To achieve such high throughput systems, high-gain phased array antennas would be desirable for achieving higher spatial coverage. In this presentation, we discuss analyzing and optimizing an aperture coupled patch antenna array with a compact feeding network for operation in 60 GHz band using Remcom’s full-wave electromagnetic simulation product, XFdtd®.
The aim of the TinyRad was to provide a platform to those potentially without in-depth RF or microwave knowledge to be able to evaluate and implement a radar system.
An engineer or software developer can use the TinyRad kit as a platform to take the supplied code and create optimised radar algorithms. The board design files are also supplied for developing the complete radar solution.
This presentation is an overview on how the TinyRad system can be used as a tool and reference design to be utilised to simplify the development of a radar solution, for a range of applications.
Phased arrays are becoming increasingly more prevalent throughout aerospace and defense and 5G. The push towards more advanced hybrid beamforming and every element digital drives channel counts of these phased arrays higher while demanding that channel density and size be reduced. The industry is moving to phased array platforms with large channel counts and needs to miniaturize channel footprint and maximize channel performance. This session will discuss a system prototyping platform (including hardware and software) that enables engineers to evaluate phased array systems with 16 transmit and 16 receive channels operating at S-Band.
This paper presents the design approach, realization and measurement results of a compact multi-stages 3-way fully integrated Doherty MMIC 40W power amplifier for 5G communication using LDMOS technology. Those results are achieved thanks to the Cds cancellation technique for the combiner design to achieve wideband impedance transformation combined with the 3-way DPA architecture to reach high efficiency and reduce load modulation. Through this paper a new coupling simulation flow is illustrated to limit risks linked to design compactness. After digital pre-distortion ACLR of -47dBc are measured for 160MHz modulated signal at 8dB OBO, while efficiency is above 46.9%.
RF front end (RFFE) has become more complex with the evolving 5G wireless standard. System-in-Package (SiP) approach to integrate multiple dies and passives into one package is a viable solution to address the RFFE challenge. However, IC design and package are typically divided efforts. Crossing the boundary is sometimes tedious and error-prone. Enabling IC designers to assess the package effect anytime in their design flow is highly desired. A fully-integrated flow with IC-package co-simulation enabled will be presented. The accelerated solver engine offers an order of magnitude speedup compared to competitor solutions. Benchmark examples demonstrate the accuracy and efficiency.
Power handling is important to consider when designing RF systems. Both active and passive devices have a role in an RF system’s power handling capabilities. That capability is a function of the device and system’s ability to dissipate heat under load. DLI, Knowles, has conducted power measurements on a range of catalog and custom designed devices. The power handling of these microwave passives have been found to be tens of watts and often exceed 40 Watts at operational temperatures of 85°C.
Many designs are accomplished with basic RF/Microwave building blocks. One of the basic building blocks often used is the quadrature hybrid couplers. It offers an equal power split between the 2 output legs which is often desired. This can be achieved in several ways which include resistive dividers, Wilkinson dividers, and quadrature hybrid couplers. Of the many ways to achieve equal power split, the most direct way to achieve a 90 degree offset is with a quadrature hybrid coupler.
Satellite based communications solutions offer the ability to provide communications coverage over large geographical areas not served by ground-based infrastructure. A number of competing architectures for implementing 3GPP standards over satellite each have with their own merits. We discuss these architectures and the challenges with their network implementation and the considerations required for deployment.
DLI has a variety of high permittivity ceramics. This allows the RF designers to create passive components that are fundamentally smaller in size than traditional industry standard ceramics like Alumina, AlN, Fused Silica, etc.
DLI not only designs single element passive components such as filters, couplers, power dividers, but they regularly integrate multiple components on a single chip. This helps to improve phase control, real estate usage, and number of parts placed on a PCB. The use of high K material also helps DLI specialize in making wideband devices where increasing the number of sections equates to broader band performance.
Impedance-matching networks ensure optimum amplifier efficiency, linearity, and noise performance, as well as maximum power delivery between components. Recent advances in network synthesis technology provide RF designers with a powerful new tool to generate optimal impedance-matching circuits that tackle aggressive performance goals. This presentation examines the challenges of meeting multiple impedance-matching circuit goals over bandwidth, with practical, physically realizable solutions using network synthesis along with commercial SMT component simulation models.
Determining exact resonator, probe and iris geometries necessary for meeting specific filter requirements frequently results in time consuming iterative design efforts. An automated tool converting coupling matrix coefficients into accurate physical dimensions proves not only beneficial for novice or casual filter designers, even seasoned developers will experience a significant reduction in design time. Mician Filter Workbench requires minimal user input and can be utilized for synthesizing Chebyshev and quasi-elliptic function filters, inline or folded, in waveguide, combline, stripline or user specific configuration.
RF Engineers direct a lot of attention to amplifier design details, and usually navigate the most difficult aspects successfully. But we often neglect to apply the same focus to the bias and decoupling components. If treated as an afterthought, these networks can cause excess noise, oscillation, low power, low gain, and non-linearities to appear in an otherwise fine effort. Through real-world examples this paper will review and illustrate typical pitfalls and highlight good design practices.
A talk about 2020 advancement made in Thin Film Technology for realization of miniature passive filters and Time Domain Solutions
Amplifier phase noise is becoming an increasingly important metric when considering low phase noise microwave systems. This seminar aims to demonstrate phase noise measurement practices that improve reliability and accuracy in an otherwise difficult measurement. Driver/DUT amplifier compression levels, power supply AM noise, harmonic filtering, proper grounding, and DUT-LO input power levels are all variables that require optimization to ensure accurate and reliable measurements. Amplifier phase noise will also be compared to oscillator phase noise, developing an intuition of when amplifier phase noise should be considered in a microwave system.
Designers are successfully simulating critical structures in silicon RFICs and PCBs using the AXIEM EM simulator. Si chips have layout features such as sub-nm z-dimensions, large via arrays in the RF path, metal mesh ground planes, and interdigitated stacked metal that cause problems for EM simulators. Complex PCB geometries typically have several signal and ground layers, many nets, and several surface-mount parts, making them challenging to simulate efficiently as well. This presentation illustrates how new features in the AXIEM simulator have been specifically developed to address these problems while maintaining simulation speed and accuracy as well as design efficiency.
As designs become more and more complicated, modern semiconductor processes are getting more complex and advanced. Sonnet addresses ease of use for EM simulation for these processes with the new and highly scalable Sonnet Technology File (.STF), which can include information needed to simulate stack-ups, metal biasing effects, per-selected settings for optimum simulation, and more. A generic PDK is presented in a .STF file, and a use case is described which can simultaneously save engineering time and eliminate potential mistakes.
The increasing complexity of integrated designs has pushed the limits of computing capabilities beyond a single CPU process. The ability to distribute circuit simulations to multiple processors on a single computer and utilizing external remote compute farms can dramatically reduce the overall simulation time for resource-intensive problems as well as optimization routines requiring hundreds if not thousands of iterations. This MicroApp will present a new option for high-performance computing for circuit simulation using AWR software solutions. Benchmark data will be presented for various sample designs.
Power amplifiers (PA) are a critical part of RF modules. Ease of performing critical measurements in PA design greatly increases design team’s productivity. Learn how to improve your critical PA measurements and corresponding analyses using Cadence Spectre RF Option and Virtuoso ADE Assembler and Explorer. We’ll demonstrate measurements like Loadpull contours, power contours, power added efficiency, small signal S-parameters, large signal S-parameters, and large signal gain. Seamless integration between Spectre RF Option and Virtuoso ADE Explorer and Assembler makes this design flow very easy to use and efficient.
FormFactor's WinCal software is a trusted software tool for achieving the best Vector Network Analyzer calibrations possible with integrated circuit wafer probes. This presentation will leave you saying "Wow, I did not know WinCal could do that!" Features such as the math scratchpad, sequencing capability, the graphing tool, and the remote API will be explained by rich examples.
Beowulf, a new fast solver that is finishing development at Sonnet, culminates years of research into a fast and reliable electromagnetic solver for large or high-frequency problems which maintains Sonnet's high level of numerical precision. Fast results are demonstrated for huge problems, solving to full numerical precision. Applications such as large 5G antenna arrays and devices are shown and discussed.
4G networks integrators are demanding multiple RF tests which require large dynamic range and versatility. The continuous evolving of LTE bands are presenting a challenge to the design engineers, in terms of multiple modulation bandwidth and wide band span from 700MHz to 6000MHz. Tests such as; Carrier Aggregation, Load-Pull, Harmonics and Jammers require digitally tunable filter solutions. This presentation will put together new block diagrams based on tunable and/or fixed filters to provide large dynamic range and versatility, which will cover:
• Tunable Frequency and Band-Width for Band-Pass and Band-Reject Filters.
• Tunable frequency of Band-Pass/Band-Stop Duplexer
S-parameter models used in high-frequency/high-speed applications continue to increase in size, complexity, and port count. By definition, a tabulated S-parameter file represents an incomplete specification of a circuit element, requiring processing of missing, noisy, and non-physical data by the simulator. Robust treatment of such models is challenging, particularly in time-domain simulators, and there is no perfect one-size-fits-all solution. Learn about our automated methodology for handling S-parameter data in the nport component. We will demonstrate recent improvements and give suggestions to more accurately and quickly simulate circuits containing S-parameter data.
As digital conversion technology continues to operate at higher frequencies, the RF front end requires less components to support the digital conversions. In many cases the ADC and DAC components can directly convert at the RF frequencies. To support this growth, low loss filters at these frequencies can reduce the RF chain between the antenna and the conversion point. The parts being offered can improve system noise performance, system sensitivity and reduce parts count with associated reliability improvements and support direct conversion close to the antenna.
Phased array antenna system have used “brick” construction methods to bring the feed network and system components into the pitch of the array for decades. With the imminent deployment of 5G phased array systems at millimeter wave frequencies, designers will migrate to the highly integrated and cost effective “panel” form. System performance while maintaining regulatory compliance will be a challenging design space. This presentation will offer a panelized array of filters which can be incorporated within the antenna array pitch and bonded to the beamforming system in panel form, enabling RF filtering.
As signal bandwidths and constellation densities of wireless standards increase, it has become increasingly important when testing an RF component to ensure that the RF performance of the test equipment used does not cause EVM measurements to be inaccurately high or low. This session will present mathematical models to quantify how the noise and distortion of the signal analyzer and signal generator affects the final EVM result. The focus will be on OFDM based standards such as WLAN-6 (802.11ax) and 5G NR.
5G devices need on-wafer source and load-pull, which can be a challenging.
Low-loss is critical to maximize the tuneable range of impedance, as is reliable pad contact during tuning.
Access to probes and tuners must be ergonomic for setup purposes as well as high power optics to deliver accurate probe placement.This is especially so if you need to evaluate harmonic tuning up to 120 GHz and over multiple temperatures.
We will discuss these problems, solved by our innovative new solution capable of tuning on both ports to 120 GHz over a broad temperature range of -40 to 125 DegC.
DLI offers an entire passive RF product line that utilizes thin film microstrip technology. This technology inherently is susceptible to unwanted crosstalk and radiation. The design and integration of DLI’s components with a PCB is critical for the success of the desired performance. This presentation will provide recommendations on mounting, channelization, and layout of devices on PCBs. Also discussed will be on chip design methods utilized by DLI to reduce the impacts of cross-talk and radiation.
The RF performance of PCB based filters is influenced by material properties and PCB fabrication processing. Depending on the filter design and construction, some of these filters have RF performance which is more sensitive to material property differences and PCB fabrication processing variation.
This presentation will show how normal variation of certain material properties can have an effect on RF performance of different types of PCB based filters. The same analogy will be done with PCB fabrication processing variables showing how they can impact the RF performance of a PCB based filter.
Phased arrays, which provide spatial power combining and beam-steering, have become the foundation for 5G mmWave deployments. In this talk, Mixcomm and Global Foundries will address the design of integrated RF SOI based mm-wave beamformers focusing on (a) impact of RF Technology choice on array module architecture, and (b) design of efficient and reliable mm-wave transmit beamformers in RF SOI. Technology choice and IC architecture/design will be presented in the context of thermal power budgets, short and long term reliability, IC packaging with antennas, and overall module cost to enable scalable, robust mm-wave arrays for dense 5G mm-wave infrastructure rollouts.
Current technological trends including 5G development create a strong need for board-level passive components at frequencies of Ka-band and above. To properly support introduction of these products at frequencies of interest, all aspects of component design and development must be considered including high frequency fixture design, installation techniques and test procedures. This forum is going to present best installation practices and test methods that would maximize performance of board-level passive chips at frequencies of Ka-Band and above.
SAGE Millimeter offers two standard dual-polarized antenna families, namely, quad-ridge based and orthomode transducer (OMT) based. The quad-ridge based antennas cover broader operating bandwidth, often multi-octave, such as 4 to 24 GHz but are limited to the lower millimeter-wave frequency due to stringent machining and assembly boundaries. The OMT based antennas draw more application attention. Various antenna types such as the conical horn, lens corrected, and scalar horn, can be used to suit any system application. Many dual-polarized antennas geared towards 5G technology have been developed by SAGE Millimeter.
The Xilinx RFSoC provides 100 Gigabit Ethernet optical ports for streaming data from its high speed A/D converters. 100 Gigabit Ethernet is capable of streaming data at rates as high as 12.5 Gigabytes per second. In order to capture data at these very high rates, real-time recording systems require a major upgrade in their storage technology. NVME provides a new storage protocol and interface to accommodate exponentially higher streaming data rates than previous generation interfaces.
This presentation will familiarize System Design Engineers with PC based real-time recording systems and the latest techniques for creating an NVME PCIe type recording system.
Characterization of Wi-Fi chipsets involves significant challenges. With channel bandwidths up to 160 MHz and MIMO architectures, the demands on test equipment are substantial. Compromises are often required involving measuring RF power per channel and time alignment between channels. Learn how to unveil the true performance of your Wi-Fi chipset.
Most noise sources in the market are powered by 28V without data transfer capability. This presentation introduce Keysight latest USB noise source that provides ease of use in powering up the noise source and facilitating data transfer. The main issue via the USB approach is the high ENR uncertainties due to unwanted heat dissipation from switching regulators, which eventually degrades the accuracy of the actual DUT noise figure measurement.This presentation will discuss methods to reduce heat dissipation and the novel technique implemented to minimize the temperature delta caused by the voltage switching regulator.
Engineers working on the characterization and validation test of 5G mmWave beamformers need a test system designed for semiconductor devices with multiple input and output ports (horizontal and vertical polarization and 4, 8, and even 16 channels).
This sessions presents a test approach that simplifies connections to the device under test, and gives users the ability to speed up measuring the TX and RX performance of every signal path, both with CW signals and with high-bandwidth 5G New Radio waveforms.
This presentation addresses FCC Part 30 and radiated tests required on 5G mmWave devices. Device positioning that meets the measurement sample grid spacing prescribed in FCC Part 30 measurements requires special consideration and advance planning. The lack of antenna ports also drives many tests that could previously be performed in a conducted environment (i.e. cabled) to be measured over-the-air. The narrow beam width and directionality of mmWave signals complicate signal capture and maximization. A positioning system applicable to radiated test chambers and specially designed for mmWave measurements is presented as a solution for FCC Part 30 and other radiated tests.
Thermoreflectance-based thermal imaging has been established as an effective technique for thermal analysis of GaN HEMTs and other high performance microwave devices. Further advances in this technique meet the increased thermal challenges with these devices with respect to thermal sensitivity and transient performance. Illumination wavelengths in the visible and near-IR range provide sub-micron spatial resolution with 50 ns transient response for top-side or back-side thermal imaging. Accurate calibration ensures a temperature resolution to 0.10 degrees C. These advances further enhance the utility of thermoreflectance-based thermal imaging to ensure long term reliability of advanced high power microwave devices.
Production testing of packaged mmWave devices using automated test equipment (ATE) presents a significant challenge. In particular, the design and construction of the tester's interface and device load board is critical to ensure reliable and repeatable test results. The seminar presents details associated with the design of the ATE interface and the device load board for supporting the testing of multi-port, beamforming mmW wave devices that operate at frequencies up to 50 GHz. In addition, an overview of the one-port Automatic Fixture Removal (AFR) calibration methodology is discussed which facilitates moving the measurement reference plane to the DUT.
Engineers always have the goal to make things smaller, lower power, and higher performance. They also tend to be lacking in time and resources. The engineering team at Richardson RFPD has teamed with Analog Devices to introduce a new highly integrated transceiver and have built a RFFE to interface with it. Our goal is to provide engineers with a small, low power, high performance starting point for their own design to reduce their design time and the amount of resources they need to do the design. This presentation will give details regarding the transceiver and RFFE
Translation loop PLLs are desired in agile RF systems that require lower jitter than the common PLL feedback divider architecture is able to achieve. Translation loop PLLs achieve around 10fs-rms jitter by replacing the PLLs feedback divider with a mixer and a high quality source. Maintaining spurious free dynamic range is also very important and it is highly possible that some spurious signals are generated in such complex sub-systems. This presentation will focus on the practical techniques to eliminate these spurious signals in translation loop PLL. Additionally a few other tricks to increase the performance will be explained.
VNAs have traditionally been single chassis instruments with embedded measurement ports. This seminar will review some application examples where modular VNA architectures provide clear advantages over single chassis systems.