A 40-GHz High Linearity Transmitter in 65-nm CMOS Technology with 32-dBm OIP3

A 65-nm CMOS transmitter composed of a high linearity I/Q up-converter and a class-A power amplifier is presented for the 5G application. To achieve high linearity, the splitting cascode topology at the transconductance (gm) stage of the up-converter is adopted. A power amplifier is cascaded to the high linearity I/Q up-converter to amplify both fundamental and intermodulation signals. The measurement results of the transmitter demonstrate a conversion gain of 18.5 dB and an output 1-dB compression point (OP1dB) of 13.5 dBm with only 22-mW dc consumption of the up-converter and 134.4 mW of the power amplifier. The two-tone measurement results exhibit two sweet-spots of third-order intermodulation (IM3). The transmitter achieves 32 dBm output third-order intercept point (OIP3) by an improvement of 9 dB. The output power of the transmitter with the third-order intermodulation distortion (IMD3) under -30 dBc is 8.6 dBm.