Exploiting On-Chip Power Management for Side-Channel Security

The high-performance and energy-efficient encryption engines have emerged as a key component for modern System-On-Chips (SoCs) in various platforms including servers, desktops, mobile, and IoT edge devices. A key bottleneck to secure operation of encryption engines is leakage of information through side-channels. For example, an adversary can extract the secret key by performing statistical analysis on measured power and electromagnetic (EM) emission signatures generated by the hardware during encryption. Countermeasures to such side-channel attacks often come at high power, area, or performance overhead. Therefore, design of side-channel secure encryption engines is a critical challenge for high-performance and/or power-/energy efficient operations. This talk will discuss that although low-power need imposes critical challenge for side-channel security, but circuit techniques traditionally developed for power management also present new opportunities for side-channel resistance. As a case-study, we show the feasibility of using integrated voltage regulator and dynamic voltage frequency scaling normally used for efficient power management, for increasing side-channel resistance of AES engines. The hardware measurement results from test-chip are presented to demonstrate the impact of power management circuits on side-channel security.