A 1.5-dB Insertion Loss, 34-dBm P1dB Power Modulator with 46% Fractional Bandwidth in 45-nm CMOS SOI
This work reports a high-power modulator implemented in 45-nm CMOS SOI for signal processing after the power amplifier. Two stacked switch variations, a 12 stack and 8 stack, were designed in 45-nm SOI CMOS and tested for trade-offs in insertion loss and power handling. These switches use a novel tapering technique to significantly improve switch linearity. The modulators have P1dB values between 34 dBm and 39 dBm while demonstrating a modulation bandwidth of nearly 500 MHz with a 1 GHz carrier. The IIP3 is between 46 dBm and 61 dBm.