System Design Considerations for Noisy Intermediate-Scale Quantum Machines
Quantum computers powered by hundreds of gate based, superconducting qubits are just over the horizon. Several groups have already announced activities on quantum processors (QP) of 50 qubits or more. The systems containing these processors will be of fundamental importance in quantum algorithm development, on our path toward quantum advantage in the noisy intermediate scale quantum (NISQ) era. Quantum advantage is the point at which quantum computers can solve a problem faster, cheaper, or more accurately than their classical counterparts, which is likely to be accomplished before fully fault tolerant machines are available.
The design of these systems requires an optimization of the limited resources available today, from materials to refrigeration, to the commercial availability of low noise RF and analog ICs that provide qubit readout and control. This talk will address the trade-offs in the design of systems based on gate based superconducting processors approaching 100 qubits. It will begin with an overview of system performance requirements as the number of qubits available for computation grows. The talk will then progress through the building blocks of the system, from the QP to the microwave interconnects to the control system, discussing the tradeoffs and limitations that exist today. It will conclude with projections on areas for future research, that will unlock the next factor of 10 increase in system computing capability.