Cryogenic CMOS Interfaces for Quantum Computers

Quantum computers rely on processing the information stored in quantum bits (qubits) that must be typically cooled well below 1 K for proper operation. Performing operations on qubits requires a classical (i.e. non-quantum) electronic interface, which is currently implemented at room temperature for the few qubits available today. However, future quantum processors will comprise thousands or even millions of qubits. To avoid the impractical requirement of thousands of cables from the cryogenic refrigerator to the room-temperature electronics, the electronic interface must operate at cryogenic temperatures as close as possible to the qubits. This talk will address the challenges of building such a scalable silicon-based cryogenic electronic interface, focusing on the use of standard CMOS technology. First, the electrical behavior of CMOS devices operating at cryogenic temperatures as low as 4 K and below will be discussed, with specific focus on the consequence for the development of compact device models usable for circuit simulation. Since the electronic interface may become the performance bottleneck as qubits keep improving, the impact of circuit non-idealities on quantum operations must be carefully assessed. This will be exemplified by showing the impact of errors in the electronic signals, such as random noise or static inaccuracies, on single-electron spin qubits. A system design methodology developed based on those results will be described, which enables the co-design of the quantum processors and the electronics and the derivation of detailed specifications for the electronics. Finally, we will demonstrate the design and the functionality of complex analog and digital systems operating at 4 K, thus demonstrating that cryogenic CMOS is a viable technology to enable large-scale quantum computing.