Scaling Up of Quantum Computers: the Importance of Interconnects and Fast Electrical Characterization

The race to a commercially significant quantum computer is akin to a modern day space race or moon shot. This emerging technology, while relying on the continued technological advancements of Moore’s Law, holds the promise of exponential speedup compared to classical computing for several algorithms. With a large scale system, a quantum computer may solve seemingly impossible tasks that are unachievable by the largest of supercomputers. These applications includes chemistry, materials, machine learning and cryptography. Today’s systems, however, are limited to 10’s of entangled quantum bits. Scaling of these small systems to more relevant sizes (i.e. > 1M qubits) is a daunting task. This talk will focus on two bottlenecks to moving beyond few-qubit devices. The first bottleneck is in the interconnect design of the quantum circuit. Today’s qubits have personalities. They are all different such that individual control of each qubit is required. A small quantum processor today has multiple RF and DC wires per qubit, which are each connected to room temperature electronics. In comparison to classical computing, this violates Rent’s Rule where the number of chip I/O ports is related to the log of the number of devices. A brute force approach to wiring will not work and a more scalable approach is needed. The second bottleneck relates to the speed of information turns in quantum development. To illustrate this point, we will talk about spin qubits which is one of the two qubit technologies in research at Intel. Fabrication of spin qubits in a silicon substrate bares similarity to conventional transistors from advanced CMOS technologies. A custom designed qubit process on a 300mm wafer from our fab has have over 10,000 individual quantum test structures. Naturally, R&D should be accelerated by the potential volume of statistical data. While automated electrical testing of a CMOS transistor wafer can be completed in less than an hour at room temperature, data collection at cryogenic temperatures is currently limited to a small number of devices with a turnaround of hours to days. Rhetorically speaking, “How can we deliver an exponentially fast compute technology with slow and serial characterization of quantum chips?” In this talk, we will introduce these two bottlenecks in more detail and cover Intel’s approach to go from the few qubit regime to a commercial scale system.