RF and DSP Techniques for Enabling Low-Cost Software-Defined RFID Readers
RFID can be thought of as an elementary backscatter method for humans to interact remotely with the physical objects around them. Since the ratification of the EPC Gen 2 specifications, the high cost of UHF RFID reader chipsets has served to hinder mass consumer adoption of this technology. However, low-cost UHF RFID readers have the potential to enable the average person to cheaply locate myriad personal effects, monitor important object metrics (such as the temperature of a coffee cup), and to uniquely annotate otherwise indistinguishable items. Due to its elementary nature, RFID practically begs to be expounded upon whether with enhanced security protocols or localization features. Pending certification, a software-defined RFID reader allows for direct lab-to-market introduction of such innovations, bypassing long and costly IC development cycles. Given these assertions, there exists a compelling need for a low-cost, software-defined solution to replace currently available UHF RFID reader ASICs. This workshop will delve into detail on two components of an effort towards such a solution: first, a low-cost subranging transmit cancellation network that, when enabled, reduces TX leakage at the SDR LNA input by 50dB; and second, a sub-2,304-logic element FPGA implementation of an EPC Gen 2 digital back end. An RFID reader will be presented that has been built around these two components, implements all mandatory EPC Gen 2 commands (except kill), and achieves an open area tag read range of 2.6m with a 1.2dBi dipole antenna and 15.2m with a 12.5dBi patch antenna.